Jobid=993ecf5e476f (0.0924)
Job Title : Senior Design Verification Engineer
Location: Leuven, Belgium/ Duisburg, Germany/ Enschede, Netherlands
Duration: 1 Year
Job Description
Key responsibilities
•Owns the verification process in the project.
•Features/Requirements extraction from the specification.
•Verification planning.
•Verification environment/testcase development.
•Responsible for the quality of the verification.
•Knowledge sharing among the design verification community and involvement in lessons learned and efficiency improvement forums.
•Contributes to the achievement of the quality objectives.
Tasks
Verification
•Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers.
•Write a verification plan using random techniques and coverage analysis, and work with designers to ensure it is complete.
•Develop tests and tune the environment to achieve coverage goals.
•Own and debug failures in simulation to root cause problems.
•Architecting, developing, and maintaining verification tools/methods to streamline the design of state-of-the-art SoCs/Chips.
•Analysis/closure of code and functional coverage.
•Work closely with architects/RTL designers to bring up a new architecture/micro-architecture on the verification environment.
•self-contained tracking of efforts.
Reporting & Communication
•reporting to team-lead and project management.
•Knowledge sharing.
•tracking of effort progress and immediate articulation of potential technical target achievement risks.
Other
•skill-related duties as assigned and according to the priorities of the moment.
Quality
•Is committed to complying with the requirements of the Quality Management System that are related to the job title and to possible changes of the system.
•Is committed to developing and implementing Cyient Quality Management System and continually improving its effectiveness.
•Uses Cyient issue tracking system to post customer complaints, non-conformities and quality improvement proposals.
Authorities
•Self-contained Digital Verification engineering work within project constraints.
Job Requirements
Education/experience:
•Master's Degree in electrical engineering or equivalent experience.
•Fundamental understanding of SoC design and CPU/DSP.
•Understanding of coverage, constrained-random, transaction level.
•Experience with System Verilog, Assertions and UVM.
•Experience with Gate level simulations.
•Experience with C/C++.
•Experience with python or a similar scripting language is a plus.
Mandatory competences
•Technical: Knowledge of digital electronics.
•Language: Fluency in English, both written and spoken.
•Personal:
oExcellent problem-solving and analytical skills.
oExcellent planning & organizing skills.
oAble to work in a team.
oStress-resistant and result-oriented.
Desirable
•Experience with low power verification (CPF/UPF).
•Experience with formal verification.
•Experience with scan/test modes verification.
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